1. Field of the Invention
The present invention relates to an electronic musical instrument which can be constituted at low cost using a system of the type in which frequency information corresponding to the note of a key is generated as a frequency number on a non-real time basis.
2. Description of the Prior Art
Heretofore, there has been employed in electronic musical instruments a system which is provided with means for generating as a frequency number, frequency information corresponding to a key and accumulates it on a real time basis, as proposed, for example, in U.S. Pat. No. 3,743,755. FIG. 1 is a block diagram showing the arrangement of such a prior art system. In FIG. 1, a frequency number (an F number) corresponding to key information derived from a key assignor 1 is read out from an F number memory 2 which is frequency number generating means, and a shift register 4 is shifted by a shift clock in synchronism with the timing at which the key information is provided. By an accumulator arranged to feed back the output from the shift register 4 to an adder 3, the F number is accumulated to obtain frequency information. In this case, the system arrangement is very simple but it has turned out that if the system is equipped with an actually required scale and functions, the cost of the shift register 4 would be unexpectedly high; hence, the conventional system is not always practical. The reason is as follows:
Consider the access time of the F number memory 2. Assuming, for example, that the sample frequency of the frequency information is 62.5 KHz, and that the key assignor 1 assigns 16 channels, for example, eight channels for an upper keyboard, seven channels for a lower keyboard and one channel for a pedal keyboard, the conventional shift register 4 is required to have 16 stages and the shift clock is of 16.times.62.5 KHz=1 MHz. Accordingly, it is desirable to execute an F number access from the F number memory 2 and the additive operation within a period of one .mu.s.
Further, for obtaining sufficient frequency accuracy, 22 or more bits, for example, 24 bits are necessary. In the case of forming a gate circuit by individual parts as of TTL, its operating speed is not so important but its cost is high. When using, for example, a master slice system of a semi-custom LSI composed of CMOS's which is considered to be less costly, a period of about 500 nanoseconds is required for the abovesaid addition, so that the F number memory 2 must be formed by an element which is of short access time and consequently expensive.
In the case where the shift register 4 is a 24-bit, 16-stage shift register and is formed as an LSI, seven gates are needed for each stage of the shift register; namely, 24.times.16.times.7=2688 gates are required in all and even these gates alone cannot be accomodated in a general purpose master slice system. If these gates are provided externally, then 48 lines, that is, 24 connection lines between the adder 3 and the shift register 4 and 24 feedback lines from the shift register 4 are connected with pins of the master slice, but the existing master slice has only about 56 pins, and hence it is short of pins as a whole and cannot be employed. With a novel master slice, the use of the semi-custom LSI loses its meaning and the cost becomes rather high.